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low-current i 2 c rtcs for high-esr crystals general description the ds1341/ds1342 low-current real-time clocks (rtcs) are timekeeping devices that provide an extremely low standby current, which permits longer life from a power supply. the ds1341/ds1342 support high-esr crystals, which broaden the pool of usable crystals for the devices. the ds1341 uses a 6pf crystal, while the ds1342 uses a 12.5pf crystal. these devices are accessed through an i 2 c serial interface. other features include two time-of-day alarms, two interrupt outputs, a programmable square- wave output, and a serial bus timeout mechanism. the clock/calendar provides seconds, minutes, hours, day, date, month, and year information. the date at the end of the month is automatically adjusted for months with fewer than 31 days, including corrections for leap year. the clock operates in either 24hr or 12hr format with an am/pm indicator. the ds1341/ds1342 also include an input for synchroni - zation. when a reference clock (e.g., 60hz power line or gps 1pps) is present at the clkin pin and the enable external clock input bit (eclk) is set to 1, the ds1341/ ds1342 rtcs are frequency-locked to the external clock and the clock accuracy is determined by the external source. in case of external clock failure, the clock is switched to the crystal oscillator. the devices are available in lead(pb)-free/rohs- compliant, 8-pin f sop or tdfn packages. the devices support a -40 n c to +85 n c extended temperature range. features s low timekeeping current of 250na (typ) s compatible with crystal esr up to 100k i s use crystals with c l = 6pf (ds1341) or c l = 12.5pf (ds1342) s +1.8v to +5.5v operating voltage range s maintain time down to +1.15v (typ) s fast (400khz) i 2 c interface s bus timeout for lockup-free operation s rtc counts seconds, minutes, hours, day, date, month, and year with leap year compensation valid through 2099 s external clock source for synchronization clock reference (e.g., 32khz, 50hz/60hz power line, gps 1pps) s two time-of-day alarms with two interrupt outputs s programmable square-wave output s industrial temperature range s small, 8-pin sop or tdfn packages applications 19-4998; rev 2; 1/12 ordering information + denotes a lead(pb)-free/rohs-compliant package. t&r = tape and reel. * ep = exposed pad. medical point of sale (pos) telematics portable instruments portable audio automotive ds1341/ds1342 scl sda clkin/inta sqw/intb x1 x2 gnd v cc v cc r pu r pu r pu cpu v cc part temp range pin- package osc c l (pf) ds1341 u+ -40 n c to +85 n c 8 f sop 6 ds1341u+t&r -40 n c to +85 n c 8 f sop 6 ds1341t+ -40 n c to +85 n c 8 tdfn-ep* 6 ds1341t+t&r -40 n c to +85 n c 8 tdfn-ep* 6 ds1342 u+ -40 n c to +85 n c 8 f sop 12.5 ds1342u+t&r -40 n c to +85 n c 8 f sop 12.5 ds1342t+ -40 n c to +85 n c 8 tdfn-ep* 12.5 ds1342t+t&r -40 n c to +85 n c 8 tdfn-ep* 12.5 ds1341/ds1342 typical operating circuit for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim integrateds website at www.maximintegrated.com.
2 stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltage range on any pin relative to ground .... -0.3v to +6.0v operating temperature range .......................... -40 n c to +85 n c junction temperature maximum ..................................... +150 n c storage temperature range ............................ -55 n c to +125 n c lead temperature (soldering, 10s) ................................ +300 n c soldering temperature (reflow) ...................................... +260 n c dc electrical characteristics (v cc = +1.8v to +5.5v, t a = -40 n c to +85 n c, unless otherwise noted.) (note 2) absolute maximum ratings note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four-layer board. for detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial . f sop junction-to-ambient thermal resistance ( b ja ) ..... 206.3 n c/w junction-to-case thermal resistance ( b jc ) ............... 42 n c/w tdfn junction-to-ambient thermal resistance ( b ja ) .......... 41 n c/w junction-to-case thermal resistance ( b jc ) ................. 8 n c/w package thermal characteristics (note 1) parameter symbol conditions min typ max units operating voltage range v cc full operation (note 3) 1.8 5.5 v v cct timekeeping (notes 3, 4) 1.3 5.5 minimum timekeeping voltage v cctmin t a = +25 n c (notes 3, 4) 1.15 1.3 v timekeeping current: ds1341 clkin = gnd or clkin = v cc (note 4) i cct v cc = +3.0v, egfil = 0, dosf = 1 220 500 na v cc = +5.5v 250 600 v cc = +3.0v, egfil = 1, dosf = 0 280 560 v cc = +5.5v 320 700 timekeeping current: ds1342 clkin = gnd or clkin = v cc (note 4) i cct v cc = +3.0v, egfil = 0, dosf = 1 250 600 na v cc = +5.5v 280 700 v cc = +3.0v, egfil = 1, dosf = 0 310 660 v cc = +5.5v 350 800 logic 1 input v ih (note 2) 0.7 x v cc v cc + 0.3 v logic 0 input v il (note 2) -0.3 0.3 x v cc v input leakage (scl, clkin/ inta ) i li eclk = 1, v in = 0v to v cc -0.1 +0.1 f a output leakage (clkin/ inta , sqw/ intb ) i o eclk = a1ie = a2ie = 0 -1.0 +1.0 f a output logic 1 v oh = +1.0v (sqw / intb ) i oh v cc r 1.8v, intcn = 0 -3.0 ma v cc r 1.3v, intcn = 0 -250 f a output logic 0 v ol = +0.4v (sda, clkin/ inta , sqw/ intb ) i ol v cc r 1.8v 3.0 ma v cc r 1.3v (note 5) 250 f a maxim integrated low-current i2c rtcs for high-esr crystals ds1341/ds1342
3 low-current i 2 c rtcs for high-esr crystals ac electrical characteristics (v cc = +1.8v to +5.5v, t a = -40 n c to +85 n c, unless otherwise noted.) (note 2, figure 1) crystal parameters note 2: limits at -40 n c are guaranteed by design; not production tested. note 3: voltage referenced to ground. note 4: specified with i 2 c bus inactive. oscillator operational, intcn = 1, eclk = 0. note 5: applies to clkin/ inta and sqw/ intb only. note 6: the minimum scl clock frequency is limited by the bus timeout feature, which resets the serial bus interface if scl is held low for t timeout . note 7: after this period, the first clock pulse is generated. note 8: a device must internally provide a hold time of at least 300ns for the sda signal (referred to the v ihmin of the scl sig - nal) to bridge the undefined region of the falling edge of scl. note 9: the maximum t hd:dat need only be met if the device does not stretch the low period (t low ) of the scl signal. note 10: a fast-mode device can be used in a standard-mode system, but the requirement t su:dat r to 250ns must then be met. this is automatically the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line t rmax + t su:dat = 1000 + 250 = 1250ns before the scl line is released. parameter symbol conditions min typ max units scl clock frequency f scl (note 6) 400 khz bus free time between a stop and start condition t buf 1.3 f s hold time (repeated) start condition t hd:sta (note 7) 0.6 f s low period of scl clock t low 1.3 f s high period of scl clock t high 0.6 f s data hold time t hd:dat (notes 8, 9) 0 0.9 f s data setup time t su:dat (note 10) 100 ns setup time for a repeated start condition t su:sta 0.6 f s rise time of both sda and scl signals t r (note 11) 20 + 0.1c b 300 ns fall time for both sda and scl signals t f (note 11) 20 + 0.1c b 300 ns setup time for stop condition t su:sto 0.6 f s capacitive load for each bus line c b (note 11) 400 pf i/o capacitance c i/o (note 12) 10 pf scl spike suppression t sp (note 12) 30 ns oscillator stop flag (osf) delay t osf (note 13) 25 100 ms timeout interval t timeout (note 14) 25 35 ms parameter symbol conditions min typ max units nominal frequency f o 32.768 khz series resistance esr 100 k i load capacitance c l ds1341 6 pf ds1342 12.5 maxim integrated ds1341/ds1342
4 note 11: c b is the total capacitance of one bus line, including all connected devices, in pf. note 12: guaranteed by design; not 100% production tested. note 13: the parameter t osf is the period of time the oscillator must be stopped for the osf flag to be set over the voltage range of 2.4v p v cc p v ccmax . note 14: the ds1341/ds1342 can detect any single scl clock held low longer than t timeoutmin . the devices i 2 c interface is in reset state and can receive a new start condition when scl is held low for at least t timeoutmax . once the device detects this condition, the sda output is released. the oscillator must be running for this function to work. figure 1. data transfer on i 2 c serial bus functional diagram scl note: timing is referenced to v ilmax and v ihmin . sda stop start repeated start t buf t hd:sta t hd:dat t su:dat t su:sto t hd:sta t sp t su:sta t high t r t f t low ds1341/ds1342 p n n n /4 /32 extsync control logic osc-1hz alarm and control registers clock and calendar registers /2 128hz osc-1hz sqw/intb clkin/inta x1 x2 scl sda 4.096khz 8.192khz 32.768khz mux/ buffer divider ext-1hz v cc serial bus interface and address register maxim integrated low-current i2c rtcs for high-esr crystals ds1341/ds1342
5 low-current i 2 c rtcs for high-esr crystals typical operating characteristics (t a = +25c, unless otherwise noted.) power-supply current vs. scl frequency ds1341/2 toc07 scl frequency (khz) supply current (a) 300 200 100 10 20 30 40 50 60 70 80 0 0 400 t a = +25c, i out = 0ma 6.0v 5.0v 3.0v 1.8v ds1341/2 toc06 output current (ma) output voltage (v) 8 6 4 2 0.1 0.2 0.3 0.4 0.5 0 01 0 sqw/intb output-voltage low vs. output current v cc = +1.8v, t a = +25c sqw/intb output-voltage high vs. output current ds1341/2 toc05 output current (ma) output voltage (v) -2 -4 -6 -8 1.0 1.2 1.4 1.6 1.8 2.0 0.8 -10 0 v cc = +1.8v, t a = +25c ds1342 i cct supply current vs. supply voltage (egfil = 1, dosf = 0) ds1341/2 toc04 supply voltage (v) supply current (na) 5 4 3 2 250 300 350 400 450 500 550 200 1 clkin = gnd, i out = 0ma +85c +25c -40c ds1342 i cct supply current vs. supply voltage (egfil = 0, dosf = 1) ds1341/2 toc03 supply voltage (v) supply current (na) 5 4 2 3 150 200 250 300 400 350 450 500 100 1 clkin = gnd, i out = 0ma +85c +25c -40c ds1341 i cct supply current vs. supply voltage (egfil = 1, dosf = 0) ds1341/2 toc02 supply voltage (v) supply current (na) 5 4 3 2 250 300 350 400 450 500 550 200 1 clkin = gnd, i out = 0ma +85c +25c -40c ds1341 i cct supply current vs. supply voltage (egfil = 0, dosf = 1) ds1341/2 toc01 supply voltage (v) supply current (na) 5 4 3 2 150 200 250 300 350 400 450 100 1 clkin = gnd, i out = 0ma +85c +25c -40c maxim integrated ds1341/ds1342
6 pin description pin configurations sop 2 7 sqw/intb x2 1 8 v cc x1 scl clkin/inta 3 6 sda ep gnd 4 5 ds1341 ds1342 ds1341 ds1342 top view + 1 3 4 8 6 5 v cc scl sda 2 7 sqw/ intb x1 x2 clkin/ inta gnd tdfn + pin name function 1 x1 connections for a standard 32.768khz quartz crystal. the internal oscillator circuitry is designed for operation with a crystal having a specified load capacitance (c l ) of 6pf (ds1341) or 12.5pf (ds1342). 2 x2 3 clkin/ inta clock input/active-low interrupt output. this i/o pin is used to output an alarm interrupt or accept an external clock input to drive the rtc counter. in the output mode, this is an open drain and requires an external pullup resistor. if not used, connect this pin to ground. 4 gnd ground 5 sda serial-data input/output. sda is the input/output pin for the i 2 c serial interface. the sda pin is open drain and requires an external pullup resistor. 6 scl serial-clock input. scl is used to synchronize data movement on the serial interface. 7 sqw/ intb square-wave/active-low interrupt output. this pin is used to output a programmable square wave or an alarm interrupt signal. this is a cmos push-pull output and does not require an external pullup resistor. if not used, this pin can be left unconnected. 8 v cc dc power input. this pin should be decoupled using a 0.01 f f or 0.1 f f capacitor. ep exposed pad (tdfn only). connect to gnd or leave unconnected. maxim integrated low-current i2c rtcs for high-esr crystals ds1341/ds1342
7 low-current i 2 c rtcs for high-esr crystals detailed description the ds1341/ds1342 low-current rtcs are timekeeping devices that consume an extremely low timekeeping cur - rent, which permits longer life from a power supply. the clock/calendar provides seconds, minutes, hours, day, date, month, and year information. the date at the end of the month is automatically adjusted for months with fewer than 31 days, including corrections for leap year through 2099. the clock operates in either a 24hr or 12hr format with an am/pm indicator. the ds1341/ds1342 use an external 32.768khz crys - tal. the oscillator circuit does not require any external resistors or capacitors to operate. the devices support a high-esr crystal, which broadens the pool of usable crystals for the device. the ds1342 uses a 12.5pf crys - tal. the ds1341 uses a 6pf crystal, which decreases oscillator current draw, but is less commonly available than the 12.5pf crystals. the ds1341/ds1342 also accept an external clock reference for synchronization. the external clock can be a 32.768khz, 50hz, 60hz, or 1hz source. when the enable oscillator bit ( eosc ) is a 0, the ds1341/ds1342 use the oscillator for timekeeping. if the enable external clock input bit (eclk) is set to 1, the time base derived from the oscillator is compared to the 1hz signal that is derived from the clkin signal. the conditioned signal drives the rtc time and date counters. if the oscillator is disabled and the clkin signal is absent, the time and date values remain static, provided that v cc remains at a valid level. when the external clock is lost or when the frequency differs more than q 0.8% from the crystal frequency, the signal derived from the crystal oscillator drives the rtc counter. when eclk is set to 0, the rtc counter is always driven with the signal derived from the crystal oscillator. when the eosc bit is a 1 and the external clock source is selected, the rtc counter is always clocked by the sig - nal from the clkin pin. address and data are transferred serially through an i 2 c serial interface. other features include two time-of-day alarms, two interrupts, a programmable square-wave output, and a bus timeout mechanism that resets the i 2 c bus if it remains inactive for a minimum of t timeout . both devices are available in lead(pb)-free/rohs- compliant, 8-pin f sop or tdfn packages, and support the -40 n c to +85 n c extended temperature range. oscillator circuit the ds1341/ds1342 use an external 32.768khz crys - tal. the oscillator circuit does not require any external resistors or capacitors to operate. the ds1341 includes integrated capacitive loading for a 6pf c l crystal, and the ds1342 includes integrated capacitive loading for a 12.5pf c l crystal. see the crystal parameters table for the external crystal parameters. the functional diagram shows a simplified schematic of the oscillator circuit. the startup time is usually less than 1 second when using a crystal with the specified characteristics. clock accuracy when running from the internal oscillator, the accuracy of the clock is dependent upon the accuracy of the crystal and the accuracy of the match between the capacitive load of the oscillator circuit and the capacitive load for which the crystal was trimmed. additional error is added by crystal frequency drift caused by temperature shifts. external circuit noise coupled into the oscillator circuit can result in the clock running fast. figure 2 shows a typical pcb layout for isolation of the crystal and oscil - lator from noise. refer to application note 58: crystal considerations with dallas real-time clocks for detailed information. figure 2. layout example crystal x1 x2 gnd local ground plane (layer 2) note: avoid routing signals in the crosshatched area (upper left-hand quadrant) of the package unless there is a ground plane between the signal line and the package. maxim integrated ds1341/ds1342
8 external synchronization when an external clock reference is used, the input from clkin/ inta is divided down to 1hz by the divi - sor selected by the clksel[2:1] bits. the 1hz from the divider (ext-1hz, see the functional diagram ) is used to correct the 1hz that is derived from the 32.768khz oscil - lator (osc-1hz). as osc-1hz drifts in relation to ext-1hz, osc-1hz is digitally adjusted. as shown in the functional diagram , the three highest frequencies driving the sqw/ intb pin are derived from the uncorrected oscillator, while the 1hz output is derived from the adjusted osc-1hz signal. conceptually, the circuit can be thought of as two 1hz signals, one derived from the internal oscillator and the other derived from the external reference clock, with the oscillator-derived 1hz signal being locked to the 1hz sig - nal derived from the external reference clock. the edges of the 1hz signals do not need to be aligned with each other. while the external clock source is present and within tolerance, the ext-1hz and osc-1hz maintain their existing lock, regardless of their edge alignment, with periodic correction of the osc- 1hz signal. if the external signal is lost and then regained sometime later, the sig - nals relock with whatever new alignment exists (figure 3). the ext-1hz is used by the device as long as it is within tolerance, which is about 0.8% of osc-1hz. while ext- 1hz is within tolerance, the skew between the two sig - nals could shift until a change of approximately 7.8ms accumulates, after which the osc-1hz signal is adjusted (figure 4). the adjustment is accomplished by digitally adjusting the 32khz oscillator divider chain. if the difference between ext-1hz and osc-1hz is greater than approximately 0.8%, osc-1hz runs unadjusted (see figure 3) and the loss of signal (los) is set, provided figure 3. loss and reacquisition of external reference clock figure 4. drift and adjustment of internal 1hz to external reference clock osc-1hz from oscillator ext-1hz from external reference skew skew break in external reference signal current lock shifted back to current lock drift after n cycles osc-1hz from oscillator ext-1hz from external reference maxim integrated low-current i2c rtcs for high-esr crystals ds1341/ds1342
9 low-current i 2 c rtcs for high-esr crystals the eclk bit is set. the external clock reference must be within the defined frequency tolerance prior to initializing the los flag. register map table 1 shows the map for the ds1341/ds1342 regis - ters. during a multibyte access, if the address pointer reaches the end of the register space (0fh), it wraps around to location 00h. on either an i 2 c start or address pointer incrementing to location 00h, the current time is transferred to a second set of registers. the time information is read from these secondary registers while the clock continues to run. this eliminates the need to reread the registers in case the main registers update during a read. i 2 c interface the i 2 c interface is guaranteed to operate when v cc is between 1.8v and 5.5v and the eosc bit is 0. the i 2 c interface is accessible whenever v cc is at a valid level. to prevent invalid device operation, the i 2 c interface should not be accessed when v cc is below +1.8v. if a microcontroller connected to the ds1341/ds1342 resets during i 2 c communications, it is possible that the microcontroller and the ds1341/ds1342 could become unsynchronized. when the microcontroller resets, the ds1341/ds1342 i 2 c interface can be placed into a known state by holding scl low for t timeout . doing so limits the minimum frequency at which the i 2 c interface can be operated. if data is being written to the device table 1. register map note: bits listed as 0 always read back as 0 and cannot be written to a 1. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 function range 00h 0 10 seconds seconds seconds 00C59 01h 0 10 minutes minutes minutes 00C59 02h 0 12/ 24 am /pm 10hr hour hours 1C12+ am /pm 00C23 10hr 03h 0 0 0 0 0 day day 1C7 04h 0 0 10 date date date 01C31 05h cent 0 0 10 mo month month/ century 01C12 + century 06h 10 year year year 00C99 07h a1m1 10 seconds seconds alarm 1 seconds 00C59 08h a1m2 10 minutes minutes alarm 1 minutes 00C59 09h a1m3 12/ 24 am /pm 10hr hour alarm 1 hours 1C12 + am /pm 00C23 10hr 0ah a1m4 dy/ dt 10 date day, date alarm 1 day, alarm 1 date 1C7 1C31 0bh a2m2 10 minutes minutes alarm 2 minutes 00C59 0ch a2m3 12/ 24 am /pm 10hr hour alarm 2 hours 1C12 + am /pm 00C23 10hr 0dh a2m4 dy/ dt 10 date day, date alarm 2 day, alarm 2 date 1C7 1C31 0eh eosc 0 egfil rs2 rs1 intcn a2ie a1ie control 0fh osf dosf los clksel2 clksel1 eclk a2f a1f control/ status maxim integrated ds1341/ds1342
10 when the interface timeout is exceeded, prior to the acknowledge, the incomplete byte of data is not written. clock and calendar (00hC06h) the time and calendar information is obtained by read - ing the appropriate register bytes. the rtc registers are illustrated in table 1. the time and calendar are set or initialized by writing the appropriate register bytes. the contents of the time and calendar registers are in the binary-coded decimal (bcd) format. the day register increments at midnight and rolls over from 7 to 1. values that correspond to the day-of-week are user-defined but must be sequential (i.e., if 1 equals sunday, then 2 equals monday, and so on). the cent bit in the month register toggles when the years register rolls over from 99 to 00. illogical time and date entries result in an unde - fined operation. the ds1341/ds1342 can be run in either 12hr or 24hr mode. bit 6 of the hours register is defined as the 12hr or 24hr mode select bit. when high, the 12hr mode is selected. in the 12hr mode, bit 5 is the am /pm bit, with a content of 1 being pm. in the 24hr mode, bit 5 is the second bit of the 10hr field. the century bit (bit 7 of the month register) is toggled when the years register incre - ments from 99 to 00. on a power-on reset (por), the time and date are set to 00:00:00 01/01/00 (hh:mm:ss dd/mm/yy) and the day register is set to 01. alarms (07hC0dh) the ds1341/ds1342 contain two time-of-day/date alarms. alarm 1 can be set by writing to registers 07hC 0ah. alarm 2 can be set by writing to registers 0bhC0dh. the alarms can be programmed to activate the clkin/ inta or sqw/ intb outputs (see table 5) on an alarm match condition. bit 7 of each of the time of day/date alarm registers are mask bits. when all the mask bits for each alarm are 0, an alarm only occurs when the values in the timekeeping registers 00hC06h match the values stored in the time of day/date alarm registers. the alarms can also be programmed to repeat every second, min - ute, hour, day, or date. tables 2 and 3 show the possible alarm settings. configurations not listed in the tables result in illogical operation. por values are undefined. the dy/ dt bits (bit 6 of the alarm day/date registers) control whether the alarm value stored in bits 0 to 5 of that register reflects the day of the week or the date of the month. if dy/ dt is written to 0, the alarm is the result of a match with date of the month. if dy/ dt is written to 1, the alarm is the result of a match with day of the week. table 2. alarm 1 mask bits table 3. alarm 2 mask bits x = dont care. x = dont care. dy/ dt alarm 1 mask bits (bit 7) alarm rate a1m4 a1m3 a1m2 a1m1 x 1 1 1 1 alarm once per second. x 1 1 1 0 alarm when seconds match. x 1 1 0 0 alarm when minutes and seconds match. x 1 0 0 0 alarm when hours, minutes, and seconds match. 0 0 0 0 0 alarm when date, hours, minutes, and seconds match. 1 0 0 0 0 alarm when day, hours, minutes, and seconds match. dy/ dt alarm 2 mask bits (bit 7) alarm rate a2m4 a2m3 a2m2 x 1 1 1 alarm once per minute (00 second of every minute). x 1 1 0 alarm when minutes match. x 1 0 0 alarm when hours and minutes match. 0 0 0 0 alarm when date, hours, and minutes match. 1 0 0 0 alarm when day, hours, and minutes match. maxim integrated low-current i2c rtcs for high-esr crystals ds1341/ds1342
11 low-current i 2 c rtcs for high-esr crystals when the rtc register values match alarm register set - tings, the corresponding alarm flag bit (a1f or a2f) is set to 1 in the control/status register. if the correspond - ing alarm interrupt enable bit (a1ie or a2ie) is also set to 1 in the control register, the alarm condition activates the output(s) defined by the eclk and intcn bits (see table 5). control register (0eh) bit 7: enable oscillator ( eosc ). when the eosc bit is 0, the oscillator is enabled. when this bit is a 1, the oscillator is disabled. this bit is cleared (0) when power is first applied. bit 6: no function bit 5: enable glitch filter (egfil). when the egfil bit is 1, the 5 f s glitch filter at the output of the crystal oscil - lator is enabled. the glitch filter is disabled when this bit is 0. disabling the glitch filter is useful in reducing power consumption. this bit is cleared (0) when power is first applied. bits 4 and 3: rate select (rs[2:1]). these bits con - trol the frequency of the square-wave output when the square wave has been enabled. table 4 shows the square-wave frequencies that can be selected with the rs bits. these bits are both set to 1 (32.768khz) when power is first applied. the 32.768khz oscillator is the source of all square-wave output frequencies. frequencies above 1hz are not con - ditioned by clkin. the 1hz output is the 32.768khz oscil - lator frequency, divided down to 1hz and conditioned by clkin, provided that the clkin frequency differs by no more than q 0.8% from the crystal frequency. cycle-to- cycle jitter of the 1hz square wave can be up to 2ms. bit 2: interrupt control (intcn). this bit controls the relationship between the two alarms and the interrupt output pins. when the intcn bit is 0, a square wave is output on the sqw/ intb pin, and the state of the eclk bit determines the function of the clkin/ inta pin (see table 5). when the intcn bit is 1 and the eclk bit is a 0, a match between the timekeeping registers and the alarm 1 registers activates the clkin/ inta pin (provided that the alarm is enabled) and a match between the timekeeping registers and the alarm 2 registers activates the sqw/ intb pin (provided that the alarm is enabled). when the intcn bit is 1 and the eclk bit is a 1, a match between the timekeeping registers and the alarm 1 registers or a match between the timekeeping registers and the alarm 2 registers activates the sqw/ intb pin (provided that the alarm is enabled). this bit is cleared (0) when power is first applied. bit 1: alarm 2 interrupt enable (a2ie). when the a2ie bit is 0, the alarm 2 interrupt function is disabled. when the a2ie bit is 1, the alarm 2 interrupt function is enabled and is routed to an output, based upon the steering defined by the intcn and eclk bits, as noted in table 5. regardless of the state of a2ie, a match between the timekeeping registers and the alarm 2 registers (0bhC0dh) sets the alarm 2 flag bit (a2f). this bit is cleared (0) when power is first applied. bit 0: alarm 1 interrupt enable (a1ie). when the a1ie bit is 0, the alarm 1 interrupt function is disabled. when the a1ie bit is 1, the alarm 1 interrupt function is enabled and is routed to an output, based upon the steering defined by the intcn and eclk bits, as noted in table 5. regardless of the state of a1ie, a match between the timekeeping registers and the alarm 1 registers (07hC 0ah) sets the alarm 1 flag bit (a1f). this bit is cleared (0) when power is first applied. control register bitmap (0eh) table 4. sqw/ intb output settings table 5. interrupt output routing bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 eosc 0 egfil rs2 rs1 intcn a2ie a1ie 0 0 0 1 1 0 0 0 rs2 rs1 sqw/ intb 0 0 1hz 0 1 4.098khz 1 0 8.192khz 1 1 32.768khz intcn eclk clkin/ inta sqw/ intb 0 0 a1f + a2f sqw 0 1 clkin input sqw 1 0 a1f a2f 1 1 clkin input a1f + a2f maxim integrated ds1341/ds1342
12 control/status register (0fh) bit 7: oscillator stop flag (osf). if the osf bit is a 1, that indicates the oscillator has stopped or was stopped for some period of time, and could be used to judge the validity of the clock and calendar data. this bit is edge triggered and is set to 1 when the internal circuitry senses the oscillator has transitioned from a normal run state to a stop condition. the following are examples of conditions that can cause the osf bit to be set: 1) power is applied for the first time. 2) the voltage present on v cc is insufficient to support oscillation. 3) the eosc bit is turned off. 4) there are external influences on the crystal (e.g., noise, leakage, etc.). this bit remains at 1 until written to 0. attempting to write osf to 1 leaves the value unchanged. bit 6: disable oscillator stop flag (dosf). this bit, when set to 1, disables the sensing of the oscillator conditions that would set the osf bit. osf remains at 0 regardless of what happens to the oscillator. this bit is cleared (0) when power is first applied. disabling the oscillator sensing is useful in reducing power consumption. bit 5: loss of signal (los). this status bit indicates the state of the clkin pin. the bit is set to 1 when the rtc counter is no longer conditioned by the external clock. this happens when eclk = 0, or when the clock signal at clkin stops toggling, or when the clkin frequency differs more than q 0.8% from the selected input fre - quency. this bit remains at 1 until written to 0. attempting to write los to 1 leaves the value unchanged. clearing the los flag when the clkin frequency is invalid inhibits subsequent detections of the input frequency deviation. bits 4 and 3: select clock source (clksel[2:1]). these two register bits select the clock source to drive the rtc counter. table 6 lists the input frequencies that can be selected. upon power-up, the bits are cleared to 0 and the 1hz rate is selected. bit 2: enable external clock input (eclk). this bit controls the direction of the clkin/ inta pin (see table 5). when the eclk bit is 1, the clkin/ inta pin is an input, with the expected input rate defined by the state of clksel2 and clksel1 (see table 6). when the eclk bit is 0, the clkin/ inta pin is an interrupt output (see table 5). if the intcn bit is 0, clkin/ inta contains the status of a1f (provided that the a1ie bit is 1) or a2f (provided that the a2ie bit is 1). if the intcn bit is 1, clkin/ inta contains the status of a1f (provided that the a1ie bit is 1). this bit is set to 0 when power is first applied. bit 1: alarm 2 flag (a2f). a 1 in the alarm 2 flag bit indicates that the time matched the alarm 2 registers. this flag can be used to generate an interrupt on either clkin/ inta or sqw/ intb depending on the status of the intcn bit in the control register. if the intcn bit is set to 0 and a2f bit is a 1 (and a2ie bit is also 1), the clkin/ inta pin goes low. if the intcn bit is set to 1 and a2f bit is 1 (and a2ie bit is also 1), the sqw/ intb pin goes low. the a2f bit is cleared when written to 0. this bit can only be written to 0. attempting to write this bit to 1 leaves the value unchanged. bit 0: alarm 1 flag (a1f). a 1 in the alarm 1 flag bit indicates that the time matched the alarm 1 registers. if the a1ie bit is also 1, the clkin/ inta pin goes low. a1f is cleared when written to 0. this bit can only be written to 0. attempting to write this bit to 1 leaves the value unchanged. control/status register bitmap (0fh) table 6. input frequency options bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 osf dosf los clksel2 clksel1 eclk a2f a1f 1 0 1 0 0 0 x x clksel2 clksel1 clkin/ inta 0 0 1hz input 0 1 50hz input 1 0 60hz input 1 1 32.768khz input maxim integrated low-current i2c rtcs for high-esr crystals ds1341/ds1342
13 low-current i 2 c rtcs for high-esr crystals i 2 c serial port operation i 2 c slave address the ds1341/ds1342s slave address byte is d0h. the first byte sent to the device includes the device identifier and the r/ w bit (figure 5). the device address sent by the i 2 c master must match the address assigned to the device. i 2 c definitions the following terminology is commonly used to describe i 2 c data transfers. master device: the master device controls the slave devices on the bus. the master device generates scl clock pulses and start and stop conditions. slave devices: slave devices send and receive data at the masters request. bus idle or not busy: time between stop and start conditions when both sda and scl are inactive and in their logic-high states. when the bus is idle, it often initiates a low-power mode for slave devices. start condition: a start condition is generated by the master to initiate a new data transfer with a slave. transitioning sda from high to low while scl remains high generates a start condition. see figure 1 for applicable timing. stop condition: a stop condition is generated by the master to end a data transfer with a slave. transitioning sda from low to high while scl remains high generates a stop condition. see figure 1 for applicable timing. repeated start condition: the master can use a repeated start condition at the end of one data transfer to indicate that it immediately initiates a new data transfer following the current one. repeated starts are commonly used during read operations to identify a specific memory address to begin a data transfer. a repeated start condition is issued iden - tically to a normal start condition. see figure 1 for applicable timing. bit write: transitions of sda must occur during the low state of scl. the data on sda must remain valid and unchanged during the entire high pulse of scl plus the setup and hold time requirements (see figure 1). data is shifted into the device during the rising edge of the scl. bit read: at the end of a write operation, the master must release the sda bus line for the proper amount of setup time (see figure 1) before the next rising edge of scl during a bit read. the device shifts out each bit of data on sda at the falling edge of the previous scl pulse and the data bit is valid at the rising edge of the current scl pulse. remember that the master generates all scl clock pulses including when it is reading bits from the slave. acknowledge (ack and nack): an acknowledge (ack) or not acknowledge (nack) is always the ninth bit transmitted during a byte transfer. the device receiving data (the master during a read or the slave during a write operation) performs an ack by transmitting a 0 during the ninth bit. a device per - forms a nack by transmitting a 1 during the ninth bit. timing for the ack and nack is identical to all other bit writes. an ack is the acknowledgment that the device is properly receiving data. a nack is used to terminate a read sequence or as an indication that the device is not receiving data. byte write: a byte write consists of 8 bits of informa - tion transferred from the master to the slave (most significant bit first) plus a 1-bit acknowledgment from the slave to the master. the 8 bits transmitted by the master are done according to the bit write definition and the acknowledgment is read using the bit read definition. byte read: a byte read is an 8-bit information transfer from the slave to the master plus a 1-bit ack or nack from the master to the slave. the 8 bits of information that are transferred (most significant bit first) from the slave to the master are read by the master using the bit read definition, and the master transmits an ack using the bit write definition to receive additional data bytes. the master must nack the last byte read to terminate communication so the slave returns control of sda to the master. slave address byte: each slave on the i 2 c bus responds to a slave address byte sent immediately following a start condition. the slave address byte contains the slave address in the most significant 7 bits and the r/ w bit in the least significant bit. the figure 5. slave address byte 1 1 1 0 r/w 0 0 0 msb lsb read/ write bit device identifier maxim integrated ds1341/ds1342
14 ds1341/ds1342s slave address is d0h and cannot be modified by the user. when the r/ w bit is 0 (such as in d0h), the master is indicating it writes data to the slave. if r/ w = 1 (d1h in this case), the master is indi - cating it wants to read from the slave. if an incorrect slave address is written, the ds1341/ds1342 assume the master is communicating with another i 2 c device and ignore the communication until the next start condition is sent. memory address: during an i 2 c write operation, the master must transmit a memory address to identify the memory location where the slave is to store the data. the memory address is always the second byte transmitted during a write operation following the slave address byte. i 2 c communication see figure 6 for an i 2 c communication example. writing a single byte to a slave: the master must generate a start condition, write the slave address byte (r/ w = 0), write the memory address, write the byte of data, and generate a stop condition. remember the master must read the slaves acknowl - edgment during all byte write operations. writing multiple bytes to a slave: to write multiple bytes to a slave, the master generates a start con - dition, writes the slave address byte (r/ w = 0), writes the starting memory address, writes multiple data bytes, and generates a stop condition. reading a single byte from a slave: unlike the write operation that uses the specified memory address byte to define where the data is to be written, the read operation occurs at the present value of the memory address counter. to read a single byte from the slave, the master generates a start condition, writes the slave address byte with r/ w = 1, reads the data byte with a nack to indicate the end of the transfer, and generates a stop condition. however, since requir - ing the master to keep track of the memory address counter is impractical, use the method for manipulat - ing the address counter for reads. manipulating the address counter for reads: a dummy write cycle can be used to force the address counter to a particular value. to do this the mas - ter generates a start condition, writes the slave address byte (r/ w = 0), writes the memory address where it desires to read, generates a repeated start condition, writes the slave address byte (r/ w = 1), figure 6. i 2 c transactions slave address start start 1 1 0 1 0 0 0 slave ack slave ack slave ack r/w msb lsb msb lsb msb lsb b7 b6 b5 b4 b3 b2 b1 b0 read/ write register address b7 b6 b5 b4 b3 b2 b1 b0 data stop single byte write -write control register to 18h multibyte write -write date register to "02" and month register to "11" single byte read -read control register multibyte read -read alarm 2 hours and date values start repeated start d1h master nack stop 1 1 0 1 0 0 0 0 0 0 0 0 1 1 1 0 0eh 1 1 0 1 0 0 0 1 1 1 0 1 0 0 0 0 0 0 0 0 1 1 1 0 d0h 0eh stop value start 1 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 d0h 04h data master nack stop value data 02h 18h example i 2 c transactions typical i 2 c write transaction 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 d0h a) c) b) d) slave ack slave ack slave ack slave ack slave ack slave ack slave ack repeated start d1h master ack 1 1 0 1 0 0 0 1 value data slave ack slave ack slave ack start 1 1 0 1 0 0 0 0 0 0 0 0 1 1 0 0 d0h 0ch slave ack slave ack stop 11h 0 0 0 1 0 0 0 1 slave ack maxim integrated low-current i2c rtcs for high-esr crystals ds1341/ds1342
15 low-current i 2 c rtcs for high-esr crystals reads data with ack or nack as applicable, and generates a stop condition. see figure 6 for a read example using the repeated start condition to specify the starting memory location. reading multiple bytes from a slave: the read operation can be used to read multiple bytes with a single transfer. when reading bytes from the slave, the master simply acks the data byte if it desires to read another byte before terminating the transaction. after the master reads the last byte it must nack to indicate the end of the transfer and then it generates a stop condition. bus timeout to avoid an unintended i 2 c interface timeout, scl should not be held low longer than t timeoutmin . the i 2 c interface is in the reset state and can receive a new start condition when scl is held low for at least t timeoutmax . when the device detects this condition, sda is released and allowed to be pulled high by the external pullup resistor. for the timeout function to work, the oscillator must be enabled and running. applications information power-supply decoupling to achieve the best results when using the ds1341/ ds1342, decouple the v cc power supply with a 0.01 f f and/or 0.1 f f capacitor. use a high-quality, ceramic, sur - face-mount capacitor if possible. surface-mount compo - nents minimize lead inductance, which improves perfor - mance, and ceramic capacitors tend to have adequate high-frequency response for decoupling applications. using open-drain outputs the clkin/ inta output is open drain and, therefore, requires an external pullup resistor to realize a logic-high output level. sda and scl pullup resistors sda is an open-drain output and requires an external pullup resistor to realize a logic-high level. because the ds1341/ds1342 do not use clock cycle stretching, a master using either an open-drain output with a pullup resistor or cmos output driver (push-pull) could be used for scl. chip information substrate connected to ground package information for the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 8 f sop u8+1 21-0036 90-0092 8 tdfn-ep t833+2 21-0137 90-0059 maxim integrated ds1341/ds1342
maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. 16 maxim integrated 160 rio robles, san jose, ca 95134 usa 1-408-601-1000 ? 2012 maxim integrated products, inc. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. revision history revision number revision date description pages changed 0 10/09 initial release 1 12/10 removed future status from the ds1342 in the ordering information table; added the package thermal characteristics section; added the ds1342 i cct parameter to the dc electrical characteristics table; changed the esr specification in the crystal parameters table from 80k w (max) to 100k w (max) and removed 35k w typ; added the tdfn package to the ordering information , pin configurations , pin description , and package information ; added the typical operating characteristics section 1, 2, 3, 5, 6, 15 2 1/12 removed future status from the tdfn packages in the ordering information table; changed the lead temperature from +260 c to +300 c in the absolute maximum ratings section; added new note 12 to the c i/o and t sp parameters in the ac electrical characteristics table; updated the time and date information on a por in the clock and calendar (00hC06h) section 1C4, 10 low-current i2c rtcs for high-esr crystals ds1341/ds1342

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